Publications

N. Afroze, H. Fahrvandi, G. Ren, P. Kumar, C. Nelson, S. Lombardo, M. Tian, P.-C. Lee, J. Chen, M. Noor, K. Chae, S. Kang, P. V. Ravindran, M. Bergschneider, G. Y. Jung, P. Omprakash, G. K. Ligonde, N. Tasneem, D. Triyoso, S. Consiglio, K. Tapily, R. Clark, G. Leusink, J. Ravichandran, S. Yu, A. Lupini, A. Kummel, K. Cho, D.-H. Choe, N. Bassiri-Gharb, J. Kacher, R. Mishra, J. H. Lee, and A. I. Khan, “Sub-nm2 ferroelectric domains via charged 180 degree walls in ZrO2,” arXiv, 2025. https://arxiv.org/abs/2507.18920

N. Afroze, S. Soliman, Y.-H. Kuo, S. Kang, M. Tian, P. Ravikumar, A. Padovani, and A. I. Khan, "Engineering Wake-Up-Free Ferroelectric Capacitors with Enhanced High-Temperature Reliability," IEEE Transactions on Device and Materials Reliability, 2026. (accepted) https://doi.org/10.1109/tdmr.2026.3679333

L. Fernandes, S. Wodzro, P. Venkatesan, P. Ravikumar, M.-Y. Lee, M. Shon, D. Chakraborty, T. Song, S. Kang, S. Soliman, M. Tian, J. Yeager, J. Adler, J. Chen, Z. Wang, D. Wolfe, S. Yu, A. Padovani, S. Datta, B. Ray, and A. I. Khan, "Enabling Radiation Hardness in Solid-State NAND Storage Utilizing a Laminated Ferroelectric Stack," Nano Letters, vol. 26, no. 10, pp. 3390–3397, 2026. https://doi.org/10.1021/acs.nanolett.5c05947

N. Afroze, J. Choi, S. Soliman, C. H. Kim, J. Chen, Y.-H. Kuo, M. Tian, C. Zhang, P. G. Ravikumar, S. Datta, A. Padovani, J. H. Lee, and A. I. Khan, "ALD-Derived WO3–x Leads to Nearly Wake-Up-Free Ferroelectric Hf0.5Zr0.5O2 at Elevated Temperatures," ACS Applied Electronic Materials, vol. 8, pp. 1681–1691, 2026. https://doi.org/10.1021/acsaelm.5c02359

T. Song, S. Kang, Y.-H. Kuo, J. Chen, L. Fernandes, N. Afroze, M. Tian, H. W. Baac, C. Shin, and A. I. Khan, “Hf/Zr Superlattice-Based High-κ Gate Dielectrics with Dipole Layer Engineering for Advanced CMOS,” ACS Nano, vol. 20, pp. 2092–2103, 2026. https://doi.org/10.1021/acsnano.5c15062

P. Venkatesan, H. Jayasankar, S. Soliman, P. Ravikumar, L. Fernandes, C. Park, A. Garlapati, C. Zhang, S. Kang, S. Yu, S. Datta, M. Tian, Z. Wang, K. Kim, K. Seo, K. Kim, W. Kim, D. Ha, L. Larche, G. Thareja, A. Padovani, and A. I. Khan, “Materials Design Principles for Large Memory Windows: Coercive Voltage Engineering in Ferroelectric–Dielectric Heterostructures,” Advanced Electronic Materials, 2026, doi: 10.1002/aelm.202500702. (Cover Article) https://doi.org/10.1002/aelm.202500702

T. Song. and A. I. Khan, “3D DRAM with stacked oxide-semiconductor channel transistors,” Nature Electronics, vol. 8, pp. 1132–1133, 2025. https://doi.org/10.1038/s41928-025-01521-z

H. J. Lee, M. Sohn, S. Yoo, Y. Lee, K. Kim, S.-G. Nam, Y. Park, S. Jo, D. Kim, J. Heo, W. Kim, D. Ha, A. Khan, S. Yu, D.-H. Choe, and S. Datta, “Laminated Ferroelectric Stack for Enhanced ISPP Slope and Endurance in FE-NAND,” IEEE Electron Device Letters, vol. 47, no. 1, pp. 188–191, 2026. https://doi.org/10.1109/led.2025.3628206

P. Venkatesan, L. Fernandes, S. Kang, P. Ravikumar, T. Song, C. Park, D. Das, K. H. P. Kim, K. Seo, K. Kim, K. Ni, A. Padovani, M. Pakala, L. Larcher, G. Thareja, W. Kim, D. Ha, and A. I. Khan, "Pushing the limits of NAND technology scaling with ferroelectrics," MRS Bulletin, vol. 50, pp. 1094–1107, 2025. https://doi.org/10.1557/s43577-025-00991-y

M. Tian, J. Cheng, N. Afroze, Y. Yang, A. I. Khan, and J. Kacher, “Ultra-thin plan-view lamella made by focused ion beam,” Ultramicroscopy, 2025, Article ID 114250. https://doi.org/10.1016/j.ultramic.2025.114250

A. Sengupta and A. I. Khan, “Editorial: Focus issue on quantum materials for neuromorphic computing,” Neuromorphic Computing and Engineering, vol. 5, p. 030201, 2025, https://doi.org/10.1088/2634-4386/adead9

M. Tian, N. Afroze, J. Kacher, and A. I. Khan, “Lift-Out Technique for Ultra-Thin Plan-View Lamella Preparation Using Focused Ion Beam,” Microscopy and Microanalysis, vol. 31, Supplement 1, pp. ozaf048–015, 2025. https://doi.org/10.1093/mam/ozaf048.015

H. Park, S. G. Kirtania, E. Sarkar, D. Chakraborty, C. Zhang, H. J. Lee, J. Shin, S. Yu, A. I. Khan, H. Kim, C. Im, M. J. Hong, D. Ha, and S. Datta, “Extreme EOT Scaling in Tungsten-Doped In2O3 MOSFETs for Enhanced Stability and Drive Current,” IEEE Transactions on Electron Devices, vol. 72, no. 12, pp. 7136–7143, 2025. https://doi.org/10.1109/ted.2025.3612345

J. Chen, Z. Wang, T. Yom, C. Zhang, M. D. Losego, and A. I. Khan, “Chemical reactions and crystallization behavior in thermal ALD of BaTiO3 thin films from bis-(1,2,4-triisopropylcyclopentadienyl)-barium and titanium isopropoxide precursors,” Journal of Vacuum Science & Technology A, vol. 43, p. 042405, 2025, https://doi.org/10.1116/6.0004385

P. Ravikumar, P. Venkatesan, C. Park, N. Afroze, M. Tian, W. Chern, S. Datta, S. Yu, S. Mahapatra, and A. I. Khan, “The First Switch Effect in Ferroelectric Field-Effect Transistors,” IEEE Transactions on Device and Materials Reliability, vol. 25, pp. 365–370, 2025. https://doi.org/10.1109/tdmr.2025.3576042

S. G. Kirtania, H. Park, O. Phadke, E. Sarkar, D. Chakraborty, F. G. Waqar, J. Shin, A. I. Khan, S. Yu, and S. Datta, “Amorphous Indium Oxide Channel FEFETs With Write Voltage of 0.9 V and Endurance >10¹² for Refresh-Free Embedded Memory,” IEEE Transactions on Electron Devices, vol. 72, no. 5, pp. 2691–2698, 2025. https://doi.org/10.1109/ted.2025.3554471

E. Sarkar, C. Zhang, D. Chakraborty, S. G. Kirtania, K. A. Aabrar, H. Park, J. Shin, H. J. Lee, M. Tian, A. I. Khan, and S. Yu, “First Demonstration of High-Performance and Extremely Stable W-Doped In2O3 Gate-All-Around (GAA) Nanosheet FET,” IEEE Transactions on Electron Devices, vol. 72, pp. 2662–2669, 2025. https://doi.org/10.1109/ted.2025.3535463

S. Woo, G. Choe, A. I. Khan, S. Datta, and S. Yu, “Design of superlattice ferroelectric-metal field-effect transistor for triple-level cell 3D NAND flash,” Microelectronic Engineering, vol. 295, p. 112276, 2025. https://doi.org/10.1016/j.mee.2024.112276

P. Venkatesan, L. Fernandes, P. Ravikumar, C. Park, Z. Wang, H. Jayasankar, A. Garlapati, T. Song, M. Tian, H. Chen, W. Chern, K. Kim, J. Woo, S. Lim, K. Kim, S. Yu, S. Datta, W. Kim, D. Ha, and A. I. Khan, “Demonstration of robust retention in band-engineered FeFETs for NAND storage applications using tunnel dielectric layer,” IEEE Electron Device Letters, vol. 46, no. 3, pp. 397–400, 2025. (Editor’s Pick). https://doi.org/10.1109/led.2024.3523235

A. H. Kashyap, P.-C. Lee, K. Chae, M. Passlack, A. K. Yadav, K. Wong, S. Nemani, E. Yieh, J. Spiegelman, K. Cho, A. I. Khan, A. C. Kummel,“Si-doped HZO and ZrO2 for hysteresis-free high-k dielectric,” Journal of Vacuum Science & Technology A, vol. 43, no. 2, pp. 022401, 2025. https://doi.org/10.1116/6.0003895

S. Woo, G. Choe, A. I. Khan, S. Datta, S. Yu, “Design of superlattice ferroelectric-metal field-effect transistor for triple-level cell 3D NAND flash,” Microelectronic Engineering, vol. 295, pp. 112276, 2025. https://doi.org/10.1016/j.mee.2024.112276

L. Fernandes, P. V. Ravindran, J. Chen, M. Tian, D. Das, H. Chen, W. Chern, K. Kim, J. Woo, S. Lim, K. Kim, W. Kim, D. Ha, S. Yu, S. Datta, A. Khan, “Optimizing memory window for ferroelectric NAND applications: An experimental study on dielectric material selection and layer positioning,” IEEE Transactions on Electron Devices, vol. 72, no. 1, pp. 234–240, 2025. https://doi.org/10.1109/ted.2024.3504475

P. Venkatesan, C. Park, T. Song, L. Fernandes, D. Das, N. Afroze, P. Ravikumar, M. Tian, H. Chen, W. Chern, K. Kim, J. Woo, S. Lim, K. Kim, W. Kim, D. Ha, S. Mahapatra, S. Yu, S. Datta, & A. Khan. “Disturb and its mitigation in Ferroelectric Field-Effect Transistors with Large Memory Window for NAND Flash Applications.” IEEE Electron Device Letters, vol. 45, no. 12, pp. 2367–2370, 2024. (Editor’s Pick). https://doi.org/10.1109/led.2024.3467210

M. Noor, M. Bergschneider, J. Kim, N. Afroze, A. I. Khan, S.-C. Chang, U. E. Avci, A. C. Kummel, K. Cho, “Nearly barrierless polarization switching mechanisms in ZrO2 having perpendicular in-plane domain walls,” ACS Applied Materials & Interfaces, vol. 16, no. 45, pp. 62282–62291, 2024. https://doi.org/10.1021/acsami.4c07728

L. Fernandes, P. V. Ravindran, T. Song, D. Das, C. Park, N. Afroze, M. Tian, H. Chen, W. Chern, K. Kim, J. Woo, S. Lim, K. Kim, W. Kim, D. Ha, S. Yu, S. Datta, & A. Khan. “Material Choices for Tunnel Dielectric Layer and Gate Blocking Layer for Ferroelectric NAND Applications.” IEEE Electron Device Letters, vol. 45, no. 10, pp. 1776–1779, 2024. https://doi.org/10.1109/led.2024.3437239

C. Park, P. V. Ravindran, D. Das, P. G. Ravikumar, C. Zhang, N. Afroze, L. Fernandes, Y. H. Kuo, J. Hur, H. Chen, M. Tian, W. Chern, S. Yu, and A. I. Khan. “Plasma-Enhanced Atomic Layer Deposition Based Ferroelectric Field-Effect Transistors.” IEEE Journal of the Electron Devices Society, vol. 12, pp. 569–572, 2024. https://doi.org/10.1109/jeds.2024.3434598

M. Passlack, N. Tasneem, C. Park, P. V. Ravindran, H. Chen, D. Das, S. Yu, E. Chen, J. F. Wang, C. S. Chang, Y. M. Lin, I. Radu, & A. Khan. “The origin of memory window closure with bipolar stress cycling in silicon ferroelectric field-effect-transistors.” Journal of Applied Physics, vol. 135, no. 13, pp. 134501–1–134501–10, 2024. https://doi.org/10.1063/5.0180919

T.-H. Kim, O. Phadke, Y.-C. Luo, H. Mulaosmanovic, J. Mueller, S. Duenkel, S. Beyer, A. Khan, S. Datta, and S. Yu. “Tunable Non-volatile Gate-to-Source/Drain Capacitance of FeFET for Capacitive Synapse.” IEEE Electron Device Letters, vol. 44, no. 10, pp. 1628–1631, 2023. https://doi.org/10.1109/led.2023.3311344

C. Park, H. Kashyap, D. Das, J. Hur, N. Tasneem, S. Lombardo, N. Afroze, W. Chern, A. C Kummel, S. Yu, & A. Khan. “Interfacial Oxide Layer Scavenging in Ferroelectric HfZrO-Based MOS Structures With Ge Channel for Reduced Write Voltages.” IEEE Transactions on Electron Devices, vol. 70, no. 8, pp. 4479–4483, 2023. https://doi.org/10.1109/ted.2023.3288510

P. V. Ravindran, P. G. Ravikumar, & A. Khan. “Conditions for Domain-Free Negative Capacitance.” IEEE Transactions on Electron Devices, vol. 70, no. 8, pp. 4493–4496, 2023. https://doi.org/10.1109/ted.2023.3278617

G. Choe, P. V. Ravindran, J. Hur, M. Lederer, A. Reck, A. Khan, and S. Yu. “Machine Learning-Assisted Statistical Variation Analysis of Ferroelectric Transistor: From Experimental Metrology to Adaptive Modeling.” IEEE Transactions on Electron Devices, vol. 70, no. 4, pp. 2015–2020, 2023. https://doi.org/10.1109/ted.2023.3244764

N. Tasneem, Z. Wang, H. Chen, S. Yu, W. Chern, & A. Khan. “Immediate Read-After-Write Capability in p-Type Ferroelectric Field-Effect Transistors and Its Evolution With Fatigue Cycling.” IEEE Transactions on Device and Materials Reliability, vol. 23, no. 1, pp. 142–146, 2023. https://doi.org/10.1109/tdmr.2023.3240319

D. Das, P. V. Ravindran, C. Park, N. Tasneem, Z. Wang, H. Chen, W. Chern, S. Yu, S. Datta, and A. I. Khan, A. “A Ge-Channel Ferroelectric Field Effect Transistor with Logic-Compatible Write Voltage.” IEEE Electron Device Letters, vol. 44, no. 2, pp. 257–260, 2023. https://doi.org/10.1109/led.2022.3231123

N. Tasneem, H. Kashyap, K. Chae, C. Park, P. C. Lee, S. F. Lombardo, N. Afroze, M. Tian, H. Kumarasubramanian, J. Hur, H. Chen, W. Chern, S. Yu, P. Bandaru, J. Ravichandran, K. Cho, J. Kacher, A. C. Kummel, and A. I. Khan. “Remote Oxygen Scavenging of the Interfacial Oxide Layer in Ferroelectric Hafnium–Zirconium Oxide-Based Metal–Oxide–Semiconductor Structures.” ACS Applied Materials & Interfaces, vol. 14, no. 38, pp. 43897–43906, 2022. https://doi.org/10.1021/acsami.2c11736

J. Hur, C. Park, G. Choe, P. Ravindran, A. I. Khan, and S. Yu, “Characterizing HfO -Based Ferroelectric 2 Tunnel Junction in Cryogenic Temperature.” IEEE Transactions on Electron Devices, vol. 69, no. 10, pp. 5948–5951, 2022. https://doi.org/10.1109/ted.2022.3200919

K. Chae, S. F. Lombardo, N. Tasneem, M. Tian, H. Kumarasubramanian, J. Hur, W. Chern, S. Yu, C. Richter, P. D. Lomenzo, M. Hoffmann, U. Schroeder, D. Triyoso, S. Consiglio, K. Tapily, R. Clark, G. Leusink, N. Bassiri-Gharb, P. Bandaru, J. Ravichandran, A. Kummel, K. Cho, J. Kacher, and A. I. Khan. “Local Epitaxial Templating Effects in Ferroelectric and Antiferroelectric ZrO2.” ACS Applied Materials & Interfaces, vol. 14, no. 32, pp. 36771–36780, 2022. https://doi.org/10.1021/acsami.2c03151

M. Hoffmann, Z. Wang, N. Tasneem, A. Zubair, P. V. Ravindran, M. Tian, A. Gaskell, D. Triyoso, S. Consiglio, K. Tapily, R. Clark, J. Hur, S. Pentapati, S. K. Lim, M. Dopita, S. Yu, W. Chern, J. Kacher, S. E. Reyes-Lillo, D. Antoniadis, J. Ravichandran, S. Slesazeck, T. Mikolajick, and A. I. Khan. “Antiferroelectric negative capacitance from a structural phase transition in zirconia.” Nature Communications, vol. 13, pp. 1–8, 2022. —Reported the discovery of negative capacitance in an antiferroelectric material. https://doi.org/10.1038/s41467-022-28860-1

Z. Wang, N. Tasneem, M. M. Islam, H. Chen, J. Hur, W. Chern, S. Yu, and A. Khan. “An Empirical Compact Model for Ferroelectric Field-Effect Transistor Calibrated to Experimental Data.” IEEE Transactions on Electron Devices, vol. 69, pp. 1519–1523, 2022. https://doi.org/10.1109/ted.2022.3146215

N. Tasneem, M. M. Islam, Z. Wang, Z. Zhao, N. Upadhyay, S. F. Lombardo, H. Chen, J. Hur, D. Triyoso, S. Consiglio, K. Tapily, R. Clark, G. Leusink, S. Kurinec, S. Datta, S. Yu, K. Ni, M. Passlack, W. Chern, and A. Khan. “Efficiency of ferroelectric field-effect transistors: An experimental study.” IEEE Transactions on Electron Devices, vol. 69, pp. 1568–1574, 2022. https://doi.org/10.1109/ted.2022.3141988

K. A. Aabrar, J. Gomez, S. G. Kirtania, M. S. Jose, Y. Luo, P. G. Ravikumar, P. V. Ravindran, H. Ye, S. Banerjee, S. Dutta, A. I. Khan, S. Yu, S. Datta. “BEOL Compatible Superlattice FEFET Analog Synapse with Improved Linearity and Symmetry of Weight.” IEEE Transactions on Electron Devices, vol. 69, pp. 2094–2100, 2022. https://doi.org/10.1109/ted.2022.3142239

J. Hur, Y.-C. Luo, A. Lu, T.-H. Wang, S. Li, A. I. Khan, and S. Yu. “Non- volatile Capacitive Crossbar Array for In-Memory Computing.” Advanced Intelligent Systems, 2100258–1–2100258-.10 (2022). https://doi.org/10.1002/aisy.202100258

A. Khan, H. J. Yoo, S. L. Shinde, P. V. Ravindran. “Materials opportunities for low-energy computing.” MRS Bulletin, vol. 46, pp. 925–929, 2021. https://doi.org/10.1557/s43577-021-00207-z

Y.-C. Luo, J. Hur, Z. Wang, W. Shim, A. I. Khan, S. Yu. “A Technology Path for Scaling Embedded FeRAM to 28 nm and Beyond With 2T1C Structure.” IEEE Transactions on Electron Devices. vol. 69, pp. 109–114, 2021. https://doi.org/10.1109/ted.2021.3131108

J. Hur, Y.-C. Luo, Z. Wang, S. Lombardo, A. I. Khan, S. Yu. “Characterizing Ferroelectric Properties of Hf0.5Zr0.5O2 from Deep-Cryogenic Temperature (4 K) to 400 K.” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 7, pp. 168–174, 2021. https://doi.org/10.1109/jxcdc.2021.3130783

N. Tasneem, Y. M. Yousry, M. Tian, M. Dopita, S. E. Reyes-Lillo, J. Kacher, N. Bassiri-Gharb, A. I. Khan. “A Janovec-Kay-Dunn-Like Behavior at Thickness Scaling in Ultra-Thin Antiferroelectric ZrO 2 Films.” Advanced Electronic Materials. vol. 7, pp. 2100485–1–2100485–9, 2021. https://doi.org/10.1002/aelm.202100485

N. E, Miller, Z. Wang, S. Dash, A. I. Khan, and S. Mukhopadhyay. “Impact of HKMG and FDSOI FeFET drain current variation in processing-in-memory architectures.” Journal of Materials Research, vol. 36, pp. 4379–4393, 2021. https://doi.org/10.1557/s43578-021-00393-1

S. F. Lombardo, M. Tian, K. Chae, J. Hur, N. Tasneem, S. Yu, K. Cho, A. C. Kummel, J. Kacher, and A. I. Khan. “Local epitaxial-like templating effects and grain size distribution in atomic layer deposited Hf0.5Zr0.5O2 thin film ferroelectric capacitors.” Applied Physics Letters, vol. 119, pp. 092901–1–092901–5, 2021. https://doi.org/10.1063/5.0057782

D. Das, and A. I. Khan. “Ferroelectricity in CMOS-Compatible Hafnium Oxides: Reviving the Ferroelectric Field-Effect Transistor Technology.” IEEE Nanotechnology Magazine, vol. 15, pp. 20–32, 2021. https://doi.org/10.1109/mnano.2021.3098218

Z. Wang, J. Hur, N. Tasneem, W. Chern, and A. I. Khan. “Extraction of Preisach model parameters for fluorite-structure ferroelectrics and antiferroelectrics.” Scientific Reports, vol. 11, pp. 1–8, 2021. https://doi.org/10.1038/s41598-021-91492-w

N. Tasneem, M. M. Islam, Z. Wang, H. Chen, J. Hur, D. Triyoso, S. Consiglio, K. Tapily, R. Clark, G. Leusink, S. Yu, W. Chern, A. I. Khan. “The impacts of ferroelectric and interfacial layer thicknesses on ferroelectric FET design.” IEEE Electron Device Letters. vol. 42, pp. 1156–1159, 2021. https://doi.org/10.1109/led.2021.3088388

C. Garg, N. Chauhan, S. Deng, A. I. Khan, S. Dasgupta, A. Bulusu, K. Ni. “Impact of random spatial fluctuationinnon-uniformcrystallinephasesonthedevicevariationofferroelectricFET.” IEEE Electron Device Letters. vol. 42, pp. 1160–1163, 2021. https://doi.org/10.1109/LED.2021.3087335

J. Hur, Y. C. Luo, N. Tasneem, A. I. Khan, S. Yu. “Ferroelectric Hafnium Zirconium Oxide Compatible With Back-End-of-Line Process.” IEEE Transactions on Electron Devices. vol. 68, pp. 3176–3180, 2021. https://doi.org/10.1109/ted.2021.3072610

G. Choe, W. Shim, P. Wang, J. Hur, A. I. Khan, S. Yu. “Impact of random phase distribution in ferroelectric transistors-based 3-D NAND architecture on In-Memory computing.” IEEE Transactions on Electron Devices. vol. 68, pp. 2543–2548, 2021. https://doi.org/10.1109/ted.2021.3068086

N. Tasneem, P. V. Ravindran, Z. Wang, J. Gomez, J. Hur, S. Yu, S. Datta, and A. I. Khan. “Differential charge boost in hysteretic ferroelectric–dielectric heterostructure capacitors at steady state.” Applied Physics Letters. 118 (12), 122901–1–122901–5 (2021). https://doi.org/10.1063/5.0035880

A. I. Khan, A. Keshavarzi, and S. Datta. “The future of ferroelectric field-effect transistor technology.” Nature Electronics, vol. 3, pp. 588–597, 2020. —Industry-focused, review article laying the promises and challenges of ferroelectric materials in advanced microelectronics for Big Data and data-centric computing applications. —Editorial at Nature Electronics: “Time to switch to ferroelectronics?”. https://doi.org/10.1038/s41928-020-00492-7

Y. C. Luo, J. Hur, P. Wang, A. I. Khan, and S. Yu. “Non-volatile,small-signal capacitance inferroelectric capacitors.” Applied Physics Letters. vol. 117, pp. 073501–1–073501–5, 2020. https://doi.org/10.1063/5.0018937

P. Wang, Z. Wang, X. Sun, J. Hur, S. Datta, A. I. Khan, S. Yu. “Investigating ferroelectric minor loop dynamics and history effect—Part II: Physical modeling and impact on neural network training.” IEEE Transactions on Electron Devices, vol. 67, pp. 3598–3604, 2020. https://doi.org/10.1109/ted.2020.3009956

P. Wang, Z. Wang, X. Sun, J. Hur, S. Datta, A. I. Khan, S. Yu. “Investigating ferroelectric minor loop dynamics and history effect—Part I: Device characterization.” IEEE Transactions on Electron Devices, vol. 67, pp. 3592–3597, 2020. https://doi.org/10.1109/ted.2020.3009623

J. Hur, N. Tasneem, G. Choe, P. Wang, Z. Wang, A. I. Khan, S. Yu. “Direct comparison of ferroelectric properties in Hf0.5Zr0.5O2 between thermal and plasma-enhanced atomic layer deposition.” Nanotechnology, vol. 31, pp. 505707, 2020. https://doi.org/10.1088/1361-6528/aba5b7

P. Wang, A. I. Khan, S. Yu. “Cryogenic behavior of NbO based threshold switching devices as oscillation 2 neurons.” Applied Physics Letters. vol. 116, pp. 162108–1–162108–5, 2020. https://doi.org/10.1063/5.0006467

P. Wang, W. Shim, Z. Wang, J. Hur, S. Datta, A. I. Khan, S. Yu. “Drain-Erase Scheme in Ferroelectric Field Effect Transistor–PartII:3-D-NANDArchitecture for In-Memory Computing.” IEEE Transactions on Electron Devices, vol. 67, pp. 962–967, 2020. https://doi.org/10.1109/ted.2020.2969383

P. Wang, W. Shim, Z. Wang, J. Hur, S. Datta, A. I. Khan, S. Yu. “Drain-Erase Scheme in Ferroelectric Field-Effect Transistor–Part I: Device Characterization.” IEEE Transactions on Electron Devices, vol. 67, pp. 955–961, 2020. https://doi.org/10.1109/ted.2020.2969401

Z. Wang, H. Ying, W. Chern, S. Yu, M. Mourigal, J. D. Cressler, and A. I. Khan. “Cryogenic characterization of a ferroelectric field-effect-transistor.” Applied Physics Letters. vol. 116, pp. 042902–1–042902–5, 2020. https://doi.org/10.1063/1.5129692

S. Pentapati, R. Perumal, S. Khandelwal, A. I. Khan, and S. K. Lim. “Optimal Ferroelectric Parameters for Negative Capacitance Field-Effect Transistors Based on Full-Chip Implementations—Part II: Scaling of the Supply Voltage.” IEEE Transactions on Electron Devices, vol. 67, pp. 371–376, 2019. https://doi.org/10.1109/ted.2019.2955010

S. Pentapati, R. Perumal, S. Khandelwal, M. Hoffmann, S. K. Lim, and A. I. Khan. “Cross-domain optimization of ferroelectric parameters for negative capacitance transistors—Part I: Constant supply voltage.” IEEE Transactions on Electron Devices, vol. 67, pp. 365–370, 2019. https://doi.org/10.1109/ted.2019.2955018

Z. Wang, and A. I. Khan. “Ferroelectric Relaxation Oscillators and Spiking Neurons.” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 5, pp. 151–157, 2019. https://doi.org/10.1109/jxcdc.2019.2928769

M. Hoffmann, P. V. Ravindran, and A. I. Khan. “Why Do Ferroelectrics Exhibit Negative Capacitance?” Materials, vol. 12, no. 22, p. 3743, 2019. (invited review). https://doi.org/10.3390/ma12223743

Y. Fang, Z. Wang, J. Gomez, S. Datta, A. I. Khan, and A. Raychowdhury, “A swarm optimization solver based on ferroelectric spiking neural networks,” Frontiers in Neuroscience, 2019. https://doi.org/10.3389/fnins.2019.00855

Y. Fang, J. Gomez, A. Wang, S. Datta, A. I. Khan, and A. Raychowdhury, “Neuro-Mimetic Dynamics of a Ferroelectric FET-Based Spiking Neuron,” IEEE Electron Device Letters, vol. 40, pp. 1213–1216, 2019. —Editor’s pick of the, 2019 issue of IEEE Electron Device Letters (vol. 40). https://doi.org/10.1109/led.2019.2914882

I. Yoon, M.-Y. Chang, K. Ni, S. Gangopadhyay, G. Smith, T. Hamam, J. Romberg, V. Narayanan, A. I. Khan, S. Datta, A. Raychowdhury, “A FerroFET-Based In-Memory Processor for Solving Distributed and Iterative Optimizations via Least-Squares Method,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2019. https://doi.org/10.1109/JXCDC.2019.2930222

Y. Long, D. Kim, E. Lee, P. Saha, B. A. Mudassar, X. She, A. I. Khan, and S. Mukhopadhyay, “A Ferroelectric FET-based Processing-in-Memory Architecture for DNN Acceleration,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2019. https://doi.org/10.1109/jxcdc.2019.2923745

A. K. Yadav, K. X. Nguyen, Z. Hong, P. Garcia-Fernandez, P. Aguado-Puente, C. T. Nelson, S. Das, B. Prasad, D. Kwon, S. Cheema, A. I. Khan, C. Hu, J. Iniguez, J. Junquera, L.-Q. Chen, D. A. Muller, R. Ramesh and S. Salahuddin, “Spatially resolved steady-state negative capacitance,” Nature, vol. 565, pp. 468–471, 2019. —Research highlight in Nature Electronics: “Negative capacitance found.” https://doi.org/10.1038/s41586-018-0855-y

Y. Liu, Z. Wang, T. Orvis, D. Sarkar, R. Kapadia, A. I. Khan, J. Ravichandran, “Epitaxial growth and dielectric characterization of atomically smooth 0.5Ba(Zr0.2Ti0.8)O3–0.5(Ba0.7Ca0.3)TiO3 thin films,” Journal of Vacuum Science & Technology A, vol. 37, pp. 011502–1–011502–6, 2019. —Cover article of January-February issue of 2019 of Journal of Vacuum Science and Technology A. https://doi.org/10.1116/1.5054130

Z. Wang, A. A. Gaskell, M. Dopita, D. Kriegner, N. Tasneem, J. Mack, N. Mukherjee, Z. Karim, and A. I. Khan. “Antiferroelectricity in lanthanum doped zirconia without metallic capping layers and post-deposition/-metallization anneals,” Applied Physics Letters, vol. 112, pp. 222902–1–222902–5, 2018. (Equal contribution by Wang and Gaskell.) —Selected as an Applied Physics Letters Editor’s pick. https://doi.org/10.1063/1.5037185

M. Hoffmann, A. I. Khan, C. Serrao, Z. Lu, S. Salahuddin, M. Pesic, S. Slesazeck, U. Schroeder, T. Mikolajick, “Ferroelectric negative capacitance domain dynamics,” Journal of Applied Physics, vol. 123, pp. 184101–1–184101–10, 2018. https://doi.org/10.1063/1.5030072

Z. Lu, C. Serrao, A. I. Khan, J. D. Clarkson, J. C. Wong, R. Ramesh and S. Salahuddin, “Electrically induced, non-volatile, metal-insulator transition in a ferroelectric-controlled MoS2 transistor,” Applied Physics Letters, vol. 112, no. 4, pp. 043107–1–043107–5, 2018. https://doi.org/10.1063/1.5005004

A. I. Khan, M. Hoffmann, K. Chatterjee, Z. Lu, R. Xu, C. Serrao, S. Smith, L. W. Martin, C. Hu, R. Ramesh, and S. Salahuddin, “Differential voltage amplification from ferroelectric negative capacitance,” Applied Physics Letters, vol. 111, pp. 253501–1–253501–5, 2017. (Equal contribution by Khan and Hoffmann.) —Cover article of Applied Physics Letters January 15, 2018 issue, selected as an Editor’s pick. https://doi.org/10.1063/1.5006958

Z. Wang, S. Khandelwal and A. I. Khan, “Ferroelectric Oscillators and Their Coupled Networks,” IEEE Electron Device Letters, vol. 38, pp. 1614–1617, 2017. https://doi.org/10.1109/led.2017.2754138

K. Chatterjee, S. Kim, G. Karbasian, A. J. Tan, A. K. Yadav, A. I. Khan, C. Hu and S. Salahuddin, “Self-Aligned, Gate Last, FDSOI, Ferroelectric Gate Memory Device With 5.5-nm Hf0.8Zr0.2O2, High Endurance and Breakdown Recovery.” IEEE Electron Device Letters, vol. 38, pp. 1379–1383, 2017. https://doi.org/10.1109/led.2017.2748992

X. Li, J. Sampson, A. I. Khan, K. Ma, S. George, A. Aziz, S. K. Gupta, S. Salahuddin, M.-F. Chang, S. Datta and V. Narayanan, “Enabling Energy-Efficient Nonvolatile Computing With Negative Capacitance FET.” IEEE Transactions on Electron Devices, vol. 64, pp. 3452–3458, 2017. https://doi.org/10.1109/ted.2017.2716338

A. I. Khan, U. Radhakrishna, S. Salahuddin & D. A. Antoniadis, “Work Function Engineering for Performance Improvement in Leaky Negative Capacitance FETs.” IEEE Electron Device Letters, vol. 38, pp. 1335–1338, 2017. https://doi.org/10.1109/led.2017.2733382

Z. Lu, C. Serrao, A. I. Khan, L. You, J. C. Wong, Y. Ye, H. Zhu, X. Zhang, and S. Salahuddin, “Nonvolatile MoS2 field effect transistors directly gated by single crystalline epitaxial ferroelectric.” Applied Physics Letters, vol. 111, pp. 023104–1–023104–5, 2017. https://doi.org/10.1063/1.4992113

S. Khandelwal, J. P. Duarte, A. I. Khan, S. Salahuddin and C. Hu, “Impact of Parasitic Capacitance and Ferroelectric Parameters on Negative Capacitance FinFET Characteristics.” IEEE Electron Device Letters, vol. 38, no. 1, pp. 142–144 (2017). https://doi.org/10.1109/led.2016.2628349

A. I. Khan, U. Radhakrishna, S. Salahuddin, and D. Antoniadis, “Negative Capacitance Behavior in a Leaky Ferroelectric,” IEEE Transactions on Electron Devices, vol. 66, pp. 4416–4422, 2016. https://doi.org/10.1109/ted.2016.2612656

M. Hoffmann, M. Pesic, K. Chatterjee, A. I. Khan, S. Salahuddin, S. Slesazeck, U. Schroeder, and T. Mikolajick, “Direct Observation of Negative Capacitance in Polycrystalline Ferroelectric HfO2.” Advanced Functional Materials, vol. 26, pp. 8643–8649, 2016. https://doi.org/10.1002/adfm.201602869

S. Bakaul, C. Serrao, M. Lee, C. W. Yeung, A. Sarker, S.-L. Hsu, A. Yadav, L. Dedon, L. You, A. I. Khan, J. Clarkson, C. Hu, R. Ramesh, S. Salahuddin, “Single crystal functional oxides on silicon,” Nature Communications, vol. 7, Article number 10547 (2016). (no page number available). https://doi.org/10.1038/ncomms10547

C.-I. Lin, A. I. Khan, S. Salahuddin and C. Hu, “Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics,” IEEE Transactions on Electron Devices, vol. 63, pp. 2197–2199, 2016. https://doi.org/10.1109/TED.2016.2514783

A. I. Khan, K. Chatterjee, J. P. Duarte, Z. Lu, A. Sachid, S. Khandelwal, R. Ramesh, C. Hu, and S. Salahuddin, “Negative capacitance in short channel FinFETs externally connected to an epitaxial ferroelectric capacitor,” IEEE Electron Device Letters, vol. 37, pp. 111–114, 2016. https://doi.org/10.1109/led.2015.2501319

A. I. Khan, X. Marti, C. Serrao, R. Ramesh and S. Salahuddin, “Voltage-Controlled Ferroelastic Switching in Pb(Zr0.2Ti0.8)O3 Thin Films,” Nano Letters, vol. 15, pp. 2229–2234, 2015. https://doi.org/10.1021/nl503806p

A. I. Khan, K. Chatterjee, B. Wang, S. Drapcho, L. You, C. Serrao, S. R. Bakaul, R. Ramesh, and S. Salahuddin. “Negative capacitance in a ferroelectric capacitor,” Nature Materials, vol. 14, pp. 182–186, 2015. —First experimental demonstration of the negative capacitance effect in a stand-alone ferroelectric thin film. —Nature Materials News and Views article: “Negative capacitance detected.” —Press coverage at the National Science Foundation, CITRIS-UC, Phys.org, etc. —Among the 9 papers cited in a 2020 Nature Materials editorial article, entitled “ A century of ferroelectricity,” highlighting some of the major advances in the field of ferroelectricity since its discovery in. 1920. https://doi.org/10.1038/nmat4148

W. Gao, A. I. Khan, X. Marti, C. Nelson, C. Serrao, J. Ravichandran, R. Ramesh, and S. Salahuddin, “Room-Temperature Negative Capacitance in a Ferroelectric–Dielectric Superlattice Heterostructure,” Nano Letters, vol. 14, pp. 5814–5819, 2014. https://doi.org/10.1021/nl502691u

A. I. Khan, P. Yu, M. Trassin, M. J. Lee, L. You, and S. Salahuddin. “The effects of strain relaxation on the dielectric properties of epitaxial ferroelectric Pb(Zr0.2Ti0.8)TiO3 thin films,” Applied Physics Letters, 105, 022903–1–022903–4 (2014). https://doi.org/10.1063/1.4885551

A. I. Khan, D. E. Nikonov, S. Manipatruni, T. Ghani, & I. A. Young, “Voltage induced magnetostrictive switching of nanomagnets: Strain assisted strain transfer torque random access memory,” Applied Physics Letters, 104, 262407–1–262407–5 (2014). https://doi.org/10.1063/1.4884419

K. Liu, D. Fu, J. Cao, J. Suh, K. X. Wang, C. Cheng, D. F. Ogletree, H. Guo, S. Sengupta, A. I. Khan, C. W. Yeung, S. Salahuddin, M. M. Deshmukh, & J. Wu, “Dense Electron System from Gate-Controlled Surface Metal–Insulator Transition,” Nano Letters, vol. 12, pp. 6272–6277, 2012. https://doi.org/10.1021/nl303379t

A. I. Khan, D. Bhowmik, P. Yu, S. J. Kim, X. Pan, R. Ramesh, and S. Salahuddin, “Experimental evidence of ferroelectric negative capacitance in nanoscale heterostructures,” Applied Physics Letters, 99, 113501–1– 113501–3 (2011). https://doi.org/10.1063/1.3634072

S. C. Kehr, Pu Yu, Y. M. Liu, M. Parzefall, A. I. Khan, R. Jacob, M. T. Wenzel, H.-G. Ribbeck, M. Helm, X. Zhang, L. M. Eng, & R. Ramesh, “Microspectroscopy on perovskite-based superlenses,” Optical Materials Express, vol. 1, pp. 1051–1060, 2011. https://doi.org/10.1364/ome.1.001051

M. K. Ashraf, A. I. Khan, & A. Haque, “Wave function penetration effects on ballistic drain current in double gate MOSFETs fabricated on (100) and (110) silicon surfaces,” Solid-State Electronics, vol. 53, pp. 271–275, 2009. https://doi.org/10.1016/j.sse.2008.12.010

A. I. Khan, M. K. Ashraf, and A. Haque, “Wave function penetration effects in double gate metal-oxide-semiconductor field-effect-transistors: impact on ballistic drain current with device scaling,” Journal of Applied Physics, vol. 105, pp. 064505–1–064505–5, 2009. https://doi.org/10.1063/1.3079518

L. Fernandes, M. Shon, P. Venkatesan, P. Ravikumar, T. Song, M. Tian, K. Kim, W. Hwang, K. Seo, S. Lim, K. Kim, W. Kim, D. Ha, A. Padovani, S. Datta, S. Yu, and A. I. Khan, "Channel-Side Interlayer Engineering in Laminated Fe-FETs: Trap-Driven Optimization of Memory Window, Retention, and Disturb in Ferroelectric NAND Flash, " The 2026 IEEE International Reliability Physics Symposium (IRPS 2026). https://doi.org/10.1109/irps61424.2026.11499225

P. Venkatesan, C. Li, A. Padovani, Z. Wang, H. Jayasankar, P. Ravikumar, M. Nabian, K. Tangsali, S. Nidhan, J. Vamaraju, R. Cherukuri, P. Mathur, E. Piccinni, R. Foiera, R. Gaffetanu, K. A. Aabrar, S. Datta, S. Kalidindi, L. Larcher, A. Khan, Y. Wang, & G. Thareja. “VLPred: Accelerated Endurance Prediction Platform Enabled by AI Surrogates.” The 2025 IEEE International Electron Devices Meeting (IEDM 2025). https://doi.org/10.1109/iedm50572.2025.11353672

P. Venkatesan, Y. Chen, T. P. O’Neill, H. L. Chan, H. Jayasankar, P. Ravikumar, Z. Wang, S. B. Fields, M. K. Lenox, W. A. Hubbard, A. Padovani, L. Larcher, G. Thareja, S. Yu, J. F. Ihlefeld, W. Kim, D. Ha, B. C. Regan, & A. Khan. “Direct Observation of Nanoscale Polarization Switching in HZO Ferroelectrics Using STEM-EBIC.” The 2025 IEEE International Electron Devices Meeting (IEDM 2025). https://doi.org/10.1109/iedm50572.2025.11353770

P. Ravikumar, A. Padovani, C. Park, P. Venkatesan, M. Desouky, S. Yu, L. Larcher, G. Thareja, K. Kim, K. Seo, K. Kim, W. Kim, W. Ha, & A. Khan. “Experimental demonstration of robust high temperature operation with 10⁴ endurance and stable V_Th at 125 °C enabled by IL scavenging in Si channel FeFETs.” The 2025 IEEE International Electron Devices Meeting (IEDM 2025). https://doi.org/10.1109/iedm50572.2025.11353477

Y.-H. Kuo, C. Zhang, P. G. Ravikumar, S. Kang, T. Song, M. A. Villena, L. Larcher, H. Kim, M. Hong, P. Yun, G. Thareja, S. Yu, D. Ha, S. Datta, J. E. Medvedeva, and A. I. Khan. “Experiments and Modeling of Defect Dynamics and BTI in Doped In2O3 TFTs Undergoing Densification during 400 °C Post-BEOL Forming Gas Annealing (FGA).” The 2025 IEEE International Electron Devices Meeting (IEDM 2025). https://doi.org/10.1109/iedm50572.2025.11353585

E. Sarkar, H. Park, M. A. A. Mamun, H. J. Lee, D. Chakraborty, E. Quezada, C. Zhang, S. G. Kirtania, M. Tian, A. I. Khan, S. Yu, K. J. Cho, H. Kim, C. Im, M. J. Hong, D. Ha, and S. Datta, “Overcoming Threshold Voltage–Performance–Stability Tradeoff with Double-Gate Gallium Doped In2O3 MOSFETs using Tri-Layer HfO2–ZrO2–HfO2 Gate Stack,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), 2025, pp. 1–4. https://doi.org/10.1109/iedm50572.2025.11353714

X. Niu, L. Fernandes, Z. Zhao, M. Jung, K. Kim, S. Lim, K. Kim, W. Kim, D. Ha, H. Mulaosmanovic, S. Duenkel, S. Beyer, V. Narayanan, A. I. Khan, and K. Ni, “Comprehensive Evaluation of Challenges in Realizing Disturb-Free Ferroelectric Vertical NAND via String-Compatible Independent Pass Gates,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), 2025, pp. 1–4. https://doi.org/10.1109/iedm50572.2025.11353563

H. J. Lee, H. Park, C. Zhang, J. Shin, E. Sarkar, H. Kim, C. Im, M. J. Hong, D. Ha, S. Yu, A. I. Khan, and S. Datta, “DC and AC PBTI/NBTI Analysis for BEOL Oxide FETs via On-the-Fly Measurement and Modeling,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), 2025, pp. 1–4. https://doi.org/10.1109/iedm50572.2025.11353777

O. Phadke, M. Shon, S. Wodzro, H. Mulaosmanovic, S. Duenkel, S. Beyer, A. I. Khan, S. Datta, and S. Yu, “On the Localized Ferroelectric Phase Variation in Scaled FeFET: Experiments and Modeling,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), 2025, pp. 1–4. https://doi.org/10.1109/iedm50572.2025.11353560

O. Phadke, J. Lee, P.-K. Hsu, C. Zhang, A. I. Khan, S. Datta, and S. Yu, “Array-Level Demonstration of Charge-Domain In-Memory Search using Back-End-of-Line Compatible Ferroelectric Nonvolatile Capacitors,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), 2025, pp. 1–4. https://doi.org/10.1109/iedm50572.2025.11353789

N. Afroze, Y.-H. Kuo, S. Kang, C. Zhang, M. Tian, S. Soliman, P. Ravikumar, S. Datta, A. Padovani, and A. I. Khan, "Wake-Up Free and Reliable 'Ready-to-Go' Ferroelectric Capacitors for High Temperature Memory-on-Logic Applications, " IEEE International Integrated Reliability Workshop (IIRW 2025), 2025. https://doi.org/10.1109/iirw66154.2025.11481740

S. Pinge, A. Moradifirouzabadi, K. Fan, P. V. Ravindran, T. H. Pantha, P.-K. Hsu, Z. Li, W. Xu, Z. Xia, F. Ponzina, W. Chern, T. Song, P. Ravikumar, M. Tian, L. Fernandes, H. Tran, H. Jayasankar, H. Chen, C. Park, A. Garlapati, K. Kim, J. Woo, S. Lim, K. Kim, W. Kim, D. Ha, D. Kuzum, S. Yu, S. Datta, A. I. Khan, T. Rosing, and M. Kang, “FeNOMS: Enhancing Open Modification Spectral Library Search with In-Storage Processing on Ferroelectric NAND (FeNAND) Flash,” in Proc. IEEE/ACM Int. Conf. on Computer-Aided Design (ICCAD), 2025. https://doi.org/10.1109/iccad66269.2025.11240813

J. Sonawane, J. Sharda, C. Park, O. Phadke, A. I. Khan, and S. Yu, “Machine Learning Assisted Compact Modeling of Dynamic Switching and Transient Response in Ferroelectric Capacitor,” in Proc. IEEE 25th Int. Conf. on Nanotechnology (NANO), Washington, DC, USA, Jul. 2025. https://doi.org/10.1109/nano63165.2025.11113805

E. Quezada, E. Sarkar, D. Chakraborty, H. Park, C. Zhang, M. Tian, A. I. Khan, and S. Datta. “Dipole Engineered Gate Stacks in AOS Channel FETs to Overcome the V_T–I_ON Tradeoff.” The 2025 Device Research Conference (DRC 2025), pages 1–2 (2025). https://doi.org/10.1109/drc66027.2025.11105736

D. Chakraborty, E. Sarkar, H. Park, H. J. Lee, E. Quezada, C. Zhang, M. Tian, A. I. Khan, and S. Datta. “Overcoming Mobility–Stability Trade-off by Gate Stack Engineering in BEOL Compatible Ga-Doped In2O3 MOSFETs.” The 2025 Device Research Conference (DRC 2025), pages 1–2 (2025). https://doi.org/10.1109/drc66027.2025.11105741

C. Park, P. Ravikumar, P. Venkatesan, L. Fernandes, S. Soliman, J. Chen, M. Shon, S. Yu, and A. I. Khan. “Endurance Enhancement in Low Operating Voltage Scavenged SOI FeFETs.” The 2025 Device Research Conference (DRC 2025), pages 1–2 (2025). https://doi.org/10.1109/drc66027.2025.11105758

M. Shon, C. Park, P. V. Ravindran, L. Fernandes, J. Lee, K. Kim, W. Hwang, K. Seo, K. Kim, W. Kim, & D. Ha. “A Comprehensive Modeling of Gate Stack Interlayer Engineering for Ferroelectric Vertical NAND.” The 2025 Device Research Conference (DRC 2025), pages 1–2 (2025). https://doi.org/10.1109/drc66027.2025.11105759

P. Venkatesan and A. I. Khan. “Ferroelectrics for Vertical NAND Flash Applications.” The 2025 IEEE International Memory Workshop (IMW 2025), pages 1–4 (2025). https://doi.org/10.1109/imw61990.2025.11026978

E. Sarkar, D. Chakraborty, W.-C. Wang, K. A. Aabrar, S. G. Kirtania, O. Phadke, C. Zhang, E. Quezada, J. Shin, S. Zhang, A. I. Khan, and S. Datta. “Analog In-Memory-Compute with Multi-bit Silicon Ferro FinFET Array for Improved Energy and Area Efficiency.” The 2025 IEEE International Memory Workshop (IMW 2025), pages 1–4 (2025). https://doi.org/10.1109/imw61990.2025.11026976

L. Fernandes, P. Venkatesan, M. Tian, Y.-H. Kuo, N. Afroze, S. Soliman, S. Kang, D. Chakraborty, T. Song, C. Zhang, K. Kim, S. Datta, and A. I. Khan. “Comparative Study of Channel Materials for Ferroelectric NAND Applications.” The 2025 IEEE International Memory Workshop (IMW 2025), pages 1–4 (2025). https://doi.org/10.1109/imw61990.2025.11026973

P. Venkatesan, A. Padovani, L. Fernandes, P. G. Ravikumar, C. Park, H. Tran, Z. Wang, H. Jayasankar, A. Garlapati, T. Song, H. Chen, W. Chern, Z. Wang, K. Kim, J. Woo, S. Lim, K. Kim, W. Kim, D. Ha, S. Yu, S. Datta, L. Larcher, G. Thareja, A. Khan, “Enhanced memory performance in ferroelectric NAND applications: The role of tunnel dielectric position for robust 10-year retention,” in Proceedings of the IEEE International Reliability Physics Symposium (IRPS), Apr. 2025. (Best student paper award) https://doi.org/10.1109/irps48204.2025.10982749

P. G. Ravikumar, A. Padovani, P. V. Ravindran, C. Park, N. Afroze, M. Tian, S. Datta, S. Yu, L. Larcher, G. Thareja, A. Khan, “Understanding correlation between memory window closure, leakage and read delay effects for FeFET reliability improvement: role of IL and FE traps,” in Proceedings of the IEEE International Reliability Physics Symposium (IRPS), Apr. 2025. https://doi.org/10.1109/irps48204.2025.10983054

A. Padovani, N. Afroze, J. Choi, Y.-H. Kuo, P. G. Ravikumar, M. Tian, P. V. Ravindran, L. Larcher, J. H. Lee, A. Khan, G. Thareja, “Multi-scale modeling-driven material to device co-optimization of ferroelectric capacitors with oxygen reservoir layer (ORL) for improved endurance,” in Proceedings of the IEEE International Reliability Physics Symposium (IRPS), Apr. 2025. https://doi.org/10.1109/irps48204.2025.10983715

N. Afroze, A. Padovani, J. Choi, P. G. Ravikumar, Y. H. Kuo, C. Zhang, T. Song, M. Tian, E. Sarkar, M. Noor, P. V. Ravindran, K. A. Aabrar, B. Yildiz, S. Mahapatra, A. Kummel, K. Cho, S. Yu, S. Datta, J. H. Lee, L. Larcher, G. Thareja, & A. Khan. “Self-Healing Ferroelectric Capacitors with 1000x Endurance Improvement at High Temperatures (85–125 °C).” The 2024 IEEE International Electron Devices Meeting (IEDM 2024), pages 4.3.1–4.3.4 (2024). https://doi.org/10.1109/iedm50854.2024.10873595

J. Lee, C. Zhang, M. Shon, J. Read, S. Deng, O. Phadke, P. V. Ravindran, M. Tian, Y.-C. Luo, T.-H. Kim, A. I. Khan, S. Datta, S. Yu, “BEOL-compatible non-volatile capacitive synapse with ALD W-Doped In2O3 semiconductor layer,” IEEE International Electron Devices Meeting (IEDM) 2024, San Francisco, USA. https://doi.org/10.1109/iedm50854.2024.10873481

E. Sarkar, C. Zhang, D. Chakraborty, F. Waqar, S. Kirtania, K. A. Aabrar, H. Park, J. Shin, M. Tian, A. I. Khan, S. Yu, S. Datta, “First Demonstration of W-Doped In2O3 Gate-All-Around (GAA) Nanosheet FET with improved performance and record threshold voltage stability,” IEEE International Electron Devices Meeting (IEDM) 2024, San Francisco, USA. https://doi.org/10.1109/iedm50854.2024.10873456

S. G. Kirtania, O. Phadke, E. Sarker, K. A. Aabrar, D. Chakraborty, F. Waqar, S. Jaewon, T. Pantha, S. Dutta, A. I. Khan, S. Yu, S. Datta, “Amorphous indium oxide channel FeFETs with write voltage of 0.9 V and endurance >10¹² for refresh-free 1T-1FeFET embedded memory,” IEEE International Electron Devices Meeting (IEDM) 2024, San Francisco, USA. https://doi.org/10.1109/iedm50854.2024.10873370

E. Sarkar, C. Zhang, D. Chakraborty, F. G. Waqar, S. Kirtania, K. A. Aabrar, H. Park, J. Shin, M. Tian, A. I. Khan, S. Yu, and S. Datta. “First Demonstration of W-doped In2O3 Gate-All-Around (GAA) Nanosheet FET with Improved Performance and Record Threshold Voltage Stability.” The 2024 IEEE International Electron Devices Meeting (IEDM 2024), (2024). https://doi.org/10.1109/iedm50854.2024.10873456

S. G. Kirtania, O. Phadke, E. Sarker, K. A. Aabrar, D. Chakraborty, F. Waqar, J. Shin, T. H. Pantha, S. Dutta, A. Khan, S. Yu, and S. Datta. “Amorphous Indium Oxide Channel FeFETs with Write Voltage of 0.9 V and Endurance >10¹² for Refresh-Free 1T-1FeFET Embedded Memory.” The 2024 IEEE International Electron Devices Meeting (IEDM 2024), (2024). https://doi.org/10.1109/iedm50854.2024.10873370

J. Lee, C. Zhang, M. Shon, J. Read, S. Deng, O. Phadke, P. V. Ravindran, M. Tian, Y. C. Luo, T. H. Kim, A. I. Khan, S. Datta, and S. Yu. “BEOL-compatible Non-Volatile Capacitive Synapse with ALD W-Doped In2O3 Semiconductor Layer.” The 2024 IEEE International Electron Devices Meeting (IEDM 2024), (2024). https://doi.org/10.1109/iedm50854.2024.10873481

D. Das, L. Fernandes, P. V. Ravindran, T. Song, C. Park, N. Afroze, M. Tian, H. Chen, K. Kim, J. Woo, S. Lim, K. Kim, W. Kim, D. Ha, S. Yu, S. Datta, & A. Khan. “Design Framework for Ferroelectric Gate Stack Engineering of Vertical NAND Structures for Efficient TLC and QLC Operation.” 2024 IEEE International Memory Workshop (IMW) (2024). https://doi.org/10.1109/imw59701.2024.10536982

P. G. Ravikumar, P. V. Ravindran, K. A. Aabrar, T. Song, S. G. Kirtania, D. Das, C. Park, N. Afroze, M. Tian, S. Yu, A. E. Islam, S. Datta, S. Mahapatra, & A. Khan. “Comprehensive time dependent dielectric breakdown (TDDB) characterization of ferroelectric capacitors under bipolar stress conditions.” The 2024 IEEE International Reliability Physics Symposium (IRPS 2024). https://doi.org/10.1109/irps48228.2024.10529414

D. Das, H. Park, Z. Wang, C. Zhang, P. Venkatesan Ravindran, C. Park, N. Afroze, P.-K. Hsu, M. Tian, H. Chen, W. Chern, S. Lim, K. Kim, K. Kim, W. Kim, D. Ha, S. Yu, S. Datta, & A. Khan, “Experimental demonstration and modeling of a ferroelectric gate stack with a tunnel dielectric insert for NAND applications.” The 2023 IEEE International Electron Devices Meeting (IEDM 2023), pages 12.4.1–12.4.4 (2023). https://doi.org/10.1109/iedm45741.2023.10413697

S. G. Kirtania, K. A. Aabrar, A. I. Khan, S. Yu, and S. Datta, “Cold-FeFET as Embedded Non-Volatile Memory with Unlimited Cycling Endurance.” The 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), (2023). https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185382

S. Woo, G. Choe, A. I. Khan, S. Datta, and S. Yu, “Design of Ferroelectric-Metal Field-Effect Transistor for Multi-Level-Cell 3D NAND Flash.” The 2023 IEEE International Memory Workshop (IMW 2023), (2023). https://doi.org/10.1109/imw56887.2023.10145961

O. Phadke, K. A. Aabrar, Y. Luo, S. G. Kirtania, A. I. Khan, S. Datta, and S. Yu, “Low-Frequency Noise Characteristics of Ferroelectric Field-Effect Transistors.”The 2023 IEEE International Reliability Physics Symposium (IRPS 2023), (2023). https://doi.org/10.1109/irps48203.2023.10117771

M. Passlack, N. Tasneem, Z. Wang, K. A. Aabrar, J. Hur, H. Chen, V. D.-H. Hou, C.-S. Chang, M.-F. Chang, S. Yu, W. Chern, S. Datta, & A. Khan, “Direct Quantitative Extraction of Internal Variables from Measured PUND Characteristics Providing New Key Insights into Physics and Performance of Silicon and Oxide Channel Ferroelectric FETs.” The IEEE International Electron Devices Meeting(IEDM 2022), pages 32.4.1–32.4.4 (2021). https://doi.org/10.1109/iedm45625.2022.10019459

Z. Wang, N. Tasneem, H. Chen, S. Yu, W. Chern, & A. Khan. “Improved Endurance with Electron-Only Switching in Ferroelectric Devices.” The 2022 Device Research Conference (DRC). https://doi.org/10.1109/drc55272.2022.9855823

G. Choe, P. V. Ravindran, A. Lu, J. Hur, M. Lederer, A. Reck, A, S. Lombardo, N. Afroze, J. Kacher, A. I. Khan, and S. Yu, “Machine Learning Assisted Statistical Variation Analysis of Ferroelectric Transistors: From Experimental Metrology to Predictive Modeling.” Proceedings of the 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), pp. 336–337 (2022). https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830392

Y. C. Luo, H. Ye, W. Chakraborty, J. Hur, P. V. Ravindran, A. I. Khan, S. Datta, and S. Yu. “Low-Frequency Noise Characteristics of BEOL-Compatible IWO Transistor.” Proceedings of the 2022 IEEE Silicon Nanoelectronics Workshop (SNW), pp. 1–2, (2022). https://doi.org/10.1109/snw56633.2022.9889056

A. A. Gaskell, Z. Wang, M. Dopita, D. Kriegner, N. Tasneem, and A. I. Khan. “The Effect of Annealing Temperature on Antiferroelectric Zirconia.” Proceedings of the 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), pp. 1–2 (2022). https://doi.org/10.1109/vlsi-tsa54299.2022.9771025

Z. Wang, N, Tasneem, J. Hur, H. Chen, S. Yu, W. Chern, and A. I. Khan. “Standby Bias Improves the Endurance in Ferroelectric Field Effect Transistors due to Fast Neutralization of Interface Traps.” Proceedings of the 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), pp. 1–2 (2022). https://doi.org/10.1109/vlsi-tsa54299.2022.9770989

N. Tasneem, Z. Wang, Z. Zhao, N. Upadhyay, S. Lombardo, H. Chen, J. Hur, D. Triyoso, S. Consiglio, K. Tapily, R. Clark, G. Leusink, S. Kurinec, S. Datta, S. Yu, K. Ni, M. Passlack, W. Chern, A. I. Khan, “Trap capture and emission dynamics in ferroelectric field-effect transistors and their impact on device operation and reliability.” The 67th IEEE International Electron Devices Meeting (IEDM 2021), pages 6.1.1–6.1.4 (2021). https://doi.org/10.1109/iedm19574.2021.9720615

Z. Wang, N. Tasneem, J. Hur, H. Chen, S. Yu, W. Chern, A. I. Khan, “Stand by bias improvement of read after write delay in ferroelectric field effect transistors.” The 67th IEEE International Electron Devices Meeting (IEDM 2021), pages 19.3.1–19.3.4 (2021). https://doi.org/10.1109/iedm19574.2021.9720502

Y.-C. Luo, J. Hur, T.-H. Wang, A. Lu, S. Li, A. I. Khan, S. Yu, “Experimental demonstration of nonvolatile capacitive crossbar array for in-memory computing.” The 67th IEEE International Electron Devices Meeting (IEDM 2021), pages 1–4 (2021). https://doi.org/10.1109/iedm19574.2021.9720508

K. A. Aabrar, J. Gomez, S. G. Kirtania, M. San Jose, Y. Luo, P. G. Ravikumar, P. V. Ravindran, H. Ye, S. Banerjee, S. Dutta, A. I. Khan, S. Yu, S. Datta, “BEOL-compatible superlattice FerroFET-based high precision analog weight cell with superior linearity and symmetry.” The 67th IEEE International Electron Devices Meeting (IEDM 2021), pages 19.6.1–19.6.4 (2021). https://doi.org/10.1109/iedm19574.2021.9720713

B. Lin, G. Choe, J. Hur, A. I. Khan, S. Yu, H. Wang. “Experimental RF Characterization of Ferroelectric Hafnium Zirconium Oxide Material at GHz for Microwave Applications.” The 2021 Device Research Conference (DRC). https://doi.org/10.1109/drc52342.2021.9467202

N. E. Miller, Z. Wang, S. Dash, A. I. Khan, S. Mukhopadhyay. “Characterization of Drain Current Variations in FeFETs for PIM-based DNN Accelerators,” The 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021. https://doi.org/10.1109/aicas51828.2021.9458437

J. Hur, Y. C. Luo, Z. Wang, W. Shim, A. I. Khan, S. Yu, “A technology path for scaling embedded FeRAM to 28nm with 2T1C structure,” The 2021 IEEE International Memory Workshop (IMW). https://doi.org/10.1109/imw51353.2021.9439624

Z. Wang, M. M. Islam, P. Wang, S. Deng, S. Yu, A. I. Khan, and K. Ni, “Depolarization field induced instability of polarization states in HfO2 based ferroelectric FETs.”The 66th International Electron Devices 2 Meeting (IEDM 2020). https://doi.org/10.1109/iedm13553.2020.9372098

J. Hur, P. Wang, Z. Wang, G. Choe, N. Tasneem, A. I. Khan, S. Yu. “Interplay of switching characteristics, cycling endurance and multilevel retention of ferroelectric capacitor.” The 66th International Electron Devices Meeting (IEDM 2020). https://doi.org/10.1109/iedm13553.2020.9372077

P. Wang, X. Peng, W. Chakraborty, A. I. Khan, S. Datta, S. Yu. “Cryogenic benchmarks of embedded memory technologies for recurrent neural network based quantum error correction.” The 66th International Electron Devices Meeting (IEDM 2020). https://doi.org/10.1109/iedm13553.2020.9371912

S. Lombardo, C. Nelson, K. Chae, S. Reyes-Lillo, M. Tian, N. Tasneem, Z. Wang, M. Hoffmann, D. Triyoso, S. Consiglio, K. Tapily, R. Clark, G. Leusink, K. Cho, A. Kummel, J. Kacher, and A. I. Khan “Atomic-scale imaging of polarization switching in an (anti-) ferroelectric memory material: Zirconia (ZrO2).” Proc. 2020 IEEE Symposium on VLSI Technology. Research highlight in Nature Electronics: “Watching anti-ferroelectrics switch for VLSI.” https://doi.org/10.1109/vlsitechnology18217.2020.9265091

Y. C. Luo, J. Hur, P. Wang, A. I. Khan, S. Yu, “Modeling multi-states in ferroelectric tunnel junction,” the 78th Device Research Conference (DRC), (2020). https://doi.org/10.1109/drc50226.2020.9135154

M. Hoffmann, P. V. Ravindran, A. I. Khan, “A microscopic “toy” model of ferroelectric negative capacitance,” The 4th IEEE Electron Devices Technology and Manufacturing Conference (EDTM) (EDTM 2020, invited paper). https://doi.org/10.1109/EDTM47692.2020.9117889

J. Gomez, S. Dutta, K. Ni, J. A. Smith, B. Grisafe, A. I. Khan and S. Datta, “Hysteresis-free negative capacitance in the multi-domain scenario for logic applications,” The 65th International Electron Devices Meeting (IEDM 2019). https://doi.org/10.1109/iedm19573.2019.8993638

P. Wang, Z. Wang, N. Tasneem, J. Hur, A. I. Khan, S. Yu. “Investigating Dynamic Minor Loop of Ferroelectric Capacitor.” The 19th Non-Volatile Memory Technology Symposium (NVMTS 2019). https://doi.org/10.1109/nvmts47818.2019.8986179

A. I. Khan. “Ferroelectrics, Negative Capacitance and Depolarization Field: What exactly is negative capacitance?” The 77th Device Research Conference (DRC) (2019). abstract/document/9046410 https://doi.org/10.1109/drc46940.2019.9046410

Z. Wang, H. Ying, N. Tasneem, A. Gaskell, J. D. Cressler, M. Mourigal, A. I. Khan, “Cryogenic Characterization of Antiferroelectric Zirconia down to 50 mK.” The 77th Device Research Conference (DRC) (2019). https://doi.org/10.1109/drc46940.2019.9046475

J. Gomez, S. Dutta, K. Ni, B. Grisafe, J. Smith, A. I. Khan and S. Datta, “Significance of Multi and Few Domain Ferroelectric Switching Dynamics for Steep-Slope Non-Hysteretic Ferroelectric Field Effect Transistor.” the 77th Device Research Conference (DRC), (2019). https://doi.org/10.1109/drc46940.2019.9046482

Z. Wang, B. Crafton, J. Gomez, R. Xu, A. Luo, Z. Krivokapic, L. Martin, S. Datta, A. Raychowdhury, A. I. Khan, “Experimental Demonstration of Ferroelectric Spiking Neurons for Unsupervised Clustering,” The 64th International Electron Devices Meeting (IEDM 2018), 13.3.1–13.3.4 (2018). https://doi.org/10.1109/iedm.2018.8614586

A. I. Khan, “On the microscopic origin of negative capacitance in ferroelectric materials: A toy model,” The 64th International Electron Devices Meeting (IEDM 2018), 9.3.1–9.3.4 (2018). (invited) https://doi.org/10.1109/iedm.2018.8614574

Y. Long, T. Na, P. Rastogi, K. Rao, A. I. Khan, S. Yalamanchili and S. Mukhopadhyay, “A ferroelectric FET-based power-efficient architecture for data-intensive computing,” Proceedings of International Conference on Computer Aided Design (ICCAD) (2018). (no page number available) https://doi.org/10.1145/3240765.3240770

N. Tasneem, A. I. Khan, “On the possibility of dynamically tuning and collapsing the ferroelectric hysteresis/memory window in an asymmetric double gate MOS device: A path to a reconfigurable logic-memory device,” Proceedings of 76th Device Research Conference (DRC) (2018). (no page number available) https://doi.org/10.1109/drc.2018.8442250

S. K. Samal, S. Khandelwal, A. I. Khan, S. Salahuddin, C. Hu, and S. K. Lim, “Full chip power benefits with negative capacitance FETs.” Proceedings of 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) (2017). (no page number available) https://doi.org/10.1109/islped.2017.8009170

G. Karbasian, A. Tan, A. Yadav, E. M. H. Sorensen, C. R. Serrao, A. I. Khan, K. Chatterjee, S. Kim, C. Hu, and S. Salahuddin, “Ferroelectricity in HfO2 thin films as a function of Zr doping.” Proceedings of 2017 Int’l Symp. VLSI Technology, Systems and Application (VLSI-TSA) (2017). (no page number available). https://doi.org/10.1109/vlsi-tsa.2017.7942488

J. P. Duarte, S. Khandelwal, A. I. Khan, A. Sachid, Y. K. Lin, H. L. Chang, S. Salahuddin and C. Hu, “Compact models of negative-capacitance FinFETs: Lumped and distributed charge models.” Proceedings of 2016 IEEE International Electron Devices Meeting (IEDM), 30.5.1-30.5.4 (2016). https://doi.org/10.1109/iedm.2016.7838514

S. George, K. Ma, A. Aziz, X. Li, J. Sampson, A. I. Khan, S. Salahuddin, S. Datta, S. Gupta, and V. Narayanan, “Nonvolatile memory design based on ferroelectric FETs,” Proceedings of 2016 53rd ACM/EDAC/IEEE Design Automation Conference (DAC) (2016). (no page number available). https://doi.org/10.1145/2897937.2898050

S. Khandelwal, A. I. Khan, J. P. Duarte, A. Sachid, S. Salahuddin, and C. Hu. “Circuit Performance Analysis of Negative Capacitance FinFETs.” Proceedings of 2016 Symposia on VLSI Technology (2016). (no page number available) https://doi.org/10.1109/vlsit.2016.7573446

A. I. Khan and S. Salahuddin, “Negative capacitance in ferroelectric materials and implications for steep transistors.” Proceedings of 2015 IEEE SOI-3D-Subthreshold Micro-electronics Technology Unified Conference (S3S) (2015). (no page number available) https://doi.org/10.7567/ssdm.2014.f-3-1

A. I. Khan, K. Chatterjee, R. Ramesh, and S. Salahuddin, “Understanding negative capacitance dynamics in ferroelectric capacitors.” Proceedings of 2015 Fourth Berkeley Symposium on Energy Efficient Electronic Systems (E3S) (2015). (no page number available) https://doi.org/10.1109/e3s.2015.7336793

C. Hu, S. Salahuddin, C.-I. Lin and A. I. Khan, “0.2 V adiabatic negative capacitance FinFET with 0.6 mA/µm I_ON and 0.1 nA/µm I_OFF,” Proceedings of 73rd Annual Device Research Conference (DRC), pp. 39–40 (2015). https://doi.org/10.1109/DRC.2015.7175542

C. Yeung, A. I. Khan, J.-Y. Cheng, S. Salahuddin and C. Hu, “Low power negative capacitance FETs for future quantum-well body technology,” Proceedings of Intl. Conf. VLSI Technology, Systems, and Applications (VLSI-TSA), (2013). (no page number available) (Best paper award.) https://doi.org/10.1109/vlsi-tsa.2013.6545648

C. Yeung, A. I. Khan, J.-Y. Cheng, S. Salahuddin and C. Hu, “Non-hysteretic negative capacitance FET with sub-30 mV/dec swing over 10⁶× current range and I_ON of 0.3 mA/µm without strain enhancement at 0.3 V,” Proceedings of Intl. Conf. Simulation of Semiconductor Processes and Devices (SISPAD), pp. 257–259 (2012). https://scholar.nycu.edu.tw/en/publications/non-hysteretic-negative-capacitance-fet-with-sub-30mvdec-swing-ov/

A. I. Khan, C. W. Yeung, C. Hu, and S. Salahuddin, “Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation,” Proceedings of Intl. Electron Devices Meeting (IEDM), 11-3-1–11-3-4 (2011). https://doi.org/10.1109/iedm.2011.6131532

A. K. Biswas, S. Chowdhury, M. M. M. Khan, M. Hasan and A. I. Khan, “Some basic ternary operations using Toffoli gates with the cost of implementation,” Proceedings of IEEE Intl. Symp. Multiple-Valued Logic (ISMVL), 142–146 (2011). https://doi.org/10.1109/ismvl.2011.34

M. M. M. Khan, A. K. Biswas, S. Chowdhury, M. Hasan and A. I. Khan, “Synthesis of GF(3)-based reversible/quantum logic circuits without garbage output,” Proceedings of IEEE Intl. Symp. Multiple-Valued Logic (ISMVL), (2009). (no page number available) https://doi.org/10.1109/ismvl.2009.73

A. I. Khan, N. Nusrat, S. M. Khan, M. Hasan, & M. H. A. Khan, “Quantum realization of some ternary circuits using Muthukrishnan-Stroud gates,” Proceedings of IEEE Intl. Symp. Multiple-Valued Logic (ISMVL), (2007). (no page number available) https://doi.org/10.1109/ismvl.2007.45